Publication Date: May 7, 2013 Edition: 2013
This book serves as a hands-on guide to timing constraints in integrated circuit design. Readers will learn to maximize performance of their IC designs, by specifying timing requirements correctly. Coverage includes key aspects of the design flow impacted by timing constraints, including synthesis, static timing analysis and placement and routing. Concepts needed for specifying timing requirements are explained in detail and then applied to specific stages in the design flow, all within the context of Synopsys Design 
Constraining Designs for Synthesis and Timing Analysis.pdf
(8.58 MB)
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| 謝謝�。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。�！ |
| 謝謝分享 |
| 做時(shí)序的，可以借鑒下！ |
| Constraining Designs for Synthesis and Timing Analysis.pdf (8.58 MB, 下載次數(shù): 24) |
| 謝謝樓主，樓主好人，一生平安。。。 |
| 后端設(shè)計(jì)的好書(shū)啊 |
| 后端好書(shū)~ |
| Constraining Designs for Synthesis and Timing Analysis.pdf (8.58 MB, 下載次數(shù): 132) |
| 謝謝樓主， |
| 謝謝樓主，樓主好人，一生平安。。。 |
