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2015年5月6號（周三），我們將在上海主辦CMOS集成電路ESD防護設計課程。詳細課程請參考附件內容，同時也可以通過點擊鏈接通過網絡注冊報名。 希望大家能帶著問題來，可以當場詢問，探討，交流，多與老師互動，同時我們也會考慮對有ESD需求的客戶安排定制的咨詢服務，可以安排上門拜訪，名額有限，時間另定。 這次ESD防護設計課程主要講授在先進工藝平臺, 高速電路, 無線界面, 特別耐高壓等設計方面, 以及在特殊環境應用領域的汽車電子, 工業產品方面的ESD問題探討和設計。通過這次課程, 讓學員更清楚得了解在高密度, 小型化, 復雜功能電子設備設計的背景下, 如何實現減少ESD 設計面積, 設計時間, 提高IC性能和完成苛刻的ESD/ LATCH-UP, EOS等各項指標的要求。隨著IC先進制程技術的應用, 芯片功能的增多和尺寸的減小, 對于半導體廠和設計公司來說, 不斷面臨著產品對靜電保護ESD提出的越來越高的要求。 這次授課老師為Bart Keppens，ESD/EOS領域的專業權威人士，豐富的工業界ESD防護設計經歷，2002年之前就職于IMEC（比利時微電子研究中心），現任Sofics 公司Director Technical Marketing。SOFICS, 作為歐洲ESD和EOS 領域的資深企業, 早已成為TSMC IP中心, 設計中心的聯盟成員, 也是UMC的合作伙伴。ESD IP覆蓋一直到了28nm的先進工藝制程，與此同時, 在新的工藝平臺SOI, 3D-IC, FINFETs方面, 公司也提出了創新的ESD解決方案。 CMOS集成電路ESD防護設計課程- Advanced ESD Protection Design in CMOS Integrated Circuits Why Participate： The course will provide an overview of the typical issues designers face when they want to protect their circuits against Electrostatic Discharge. Through a set of basic and advanced case studies different on-chip ESD protection concepts are compared. IC designers continue to combine ever more features in advanced digital Systems-on-Chips (SoCs) like analog to digital and digital to analog conversion, sensor interfaces, audio/video handling, high speed interfaces, optical links... The design of these circuits is complex and involves combining IP blocks from different sources. On top of this functional design complexity, circuit designers face challenges related to ESD protection: on-chip ESD concepts used in general purpose I/O’s are not well suited for many specialty interfaces because they introduce high parasitic capacitance, series resistance and leakage current. Similar problems exist in BCD platforms for automotive applications and other high voltage applications. E.g. the amount of electronic circuits in cars has been steadily increasing to an average of more than 50 ASICs per car. Not only the number of circuits in cars has been expanding. Also the quality requirements have been continuously increasing. While on-chip ESD requirements are being lowered in consumer electronics the specifications for automotive parts have only been increased. LIN/CAN interfaces for instance must pass stringent system level ESD stress (IEC 61000-4-2) of more than 6kV. This increased requirement strongly limits the options for ESD protection. Furthermore there are many non-ESD requirements that affect the selection of the most appropriate ESD concept: Electrical OverStress (EOS), Electromagnetic compatibility (EMC) and of course (transient) latch-up. Drastic changes to the process platform (SOI, 3D-IC, FinFETS) can also cause new ESD challenges.
This course has been developed for several categories of designers: * Managers of design teams of ESD/EMC, analog IP blocks and circuits, and their designers. * ESD Specialist/Engineer、 Engineers correlated with Engineering/Quality、System Engineer * Designers with ESD experience, to update their ESD knowledge and to tune their experience to the present-day design procedures.
Lynne Consulting is offering advanced engineering courses in the field of analog, RF and mixed-signal IC design targeting the audience of electrical engineers, company managers and marketing engineers working in the semiconductor industry. The lecturers are leading practitioners and top experts in the area from high-technology companies and universities, who teach the most up-to-date information available at the time of the course. Course Details： * Duration: 1 day（6th May 2015） *Location：Building 21, No 1388, Zhangdong Road, Pudong New District, Shanghai, China * Fees:￥1200/person，A discount applies for groups before 22nd April 2015 （2 persons（Total：￥2180）；3 persons（Total：￥3100）；4 persons or more（negotiation）） * ￥800/person for students * The above discount can not apply simultaneously *Contact us：(Steven.Yu,021-58978665,Email:steven.yu@lynneconsulting.com) The Course Schedule: THEME 1:Introduction - Reason for On-chip ESD protection THEME 2:ESD design window - Concept - ESD test models THEME 3:ESD protection approach overview - Device types - Protection concepts THEME 4:ESD protection for advanced CMOS - Analog interfaces - Advanced CMOS nodes - High voltage tolerant interfaces - Wireless interfaces - High speed interfaces - ESD protection in SOI processes - Sofics approach and track records
- ESD protection in high voltage - Automotive, industrial applications - Sofics approach and track records
- Summary - Trends - Tools - Conclusions Lecturer’s Biography:
From May 2002 he joined Sarnoff Europe, Belgium, solving ESD related problems for customers worldwide, first as ESD engineer, later as technical leader, ESD design specialist. From 2006, Bart supports the Business Development initiatives as Technical Director for ESD. After a management buy-out in June 2009, Sarnoff Europe became 'SOFICS - Solutions for ICs' where Bart is Director Technical Marketing working with semiconductor companies worldwide. Bart (co-) authored more than 25 peer-reviewed published articles in the field of ‘on-chip ESD protection and testing’ and ‘Non Volatile Memories’. Invited papers on ESD solutions and TLP analysis techniques have been delivered at the RCJ ESD symposium in Japan every year between 2006 - 2012. He is member of the Technical Program Committee (‘TPC’) of the EOS/ESD symposium since 2003, member of the ESREF TPC in 2003, 2005, 2007, 2009 and 2010 and member of the Taiwan ESD and Reliability conference TPC since 2010. Bart acted as a Workshop Panelist on ESD topics during various conferences (EOS/ESD Symposium and RCJ) and presented invited tutorials at Taiwan ESD and Reliability conference in 2008, 2010 and 2012. Bart holds several on-chip ESD protection design patents. About Sofics: Sofics is the world leader in on-chip electrostatic discharge (ESD) and electrical overstress (EOS) solutions for ICs. Our technology is proven in all of the world’s major foundries and process nodes, and has been successfully implemented in over a thousand chip designs from IC companies of all sizes. Our TakeCharge portfolio of on-chip solutions offers unique advantages in any IC design requiring custom or specialty I/Os, from 0.18um down to 28nm. TakeCharge technology enables twice the I/O performance in applications that run at high frequencies or high speeds. In low-power applications it delivers ESD protection with leakage that is orders of magnitude lower than generic solutions. When applications call for more robust ESD/EOS protection, TakeCharge outperforms all other approaches while occupying far less silicon area. Sofics also offers PowerQubic technology, a breakthrough in delivering robust on-chip EOS solutions in high-voltage applications. PowerQubic handles all system-level ESD/EOS requirements. We also partner with other IC experts to develop integrated design solutions for specialized applications CustomIO. Sofics recently collaborated with ICsense to build a stable, fully ESD- protected I/O in both 40nm and 28nm that interfaces 1.8V gates with legacy 3.3V off-chip devices. Sofics solutions are highly cost-effective. An IP license from Sofics is more economical than adding staff to an ESD department or hiring a consultant. It is also more cost-efficient than buying shuttle space to develop alternative solutions. Since our solutions are foundry and field-proven, licensees get IP that works the first time. This eliminates the need for expensive re-spins and gets the product to market faster. With our large and growing portfolio of patented IP, in most cases the precise ESD/EOS solution you need will be available off the shelf. Our TakeCharge customers include many of the world’s leading IC makers, and our PowerQubic portfolio has been licensed by a top tier foundry to offer to their customers.
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