module traffic(clk,led);
input clk;
output led;
reg [31:0]cnt;
reg clock;
reg [2:0]led=3'b000;
reg flag=0;
reg dengf=0;
reg count;
//////////////分頻至1HZ/////////////////
always @(posedge clk)
begin
if (cnt=='d25000000)
begin
clock<=~clock;
cnt<=0;
//led<=~led;
end
else
cnt<=cnt+1;
end
/*
////////////延時//////////////////////
always @(posedge clock )
begin
if(flag==1)
if(count<=5) count<=count+1;
else
begin
flag=0;
dengf=1;
count=0;
end
end
always
begin
led[2]=1;
flag=1;
while(!dengf);
dengf=0;
led[2]=0;
led[1]=1;
flag=1;
while(!dengf);
dengf=0;
led[2]=0;
led[0]=1;
flag=1;
while(!dengf);
dengf=0;
led[2]=0;
end
endmodule
下載后led[2]熄滅,led[1]和led[0]點亮。 |