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總結(jié)
對(duì)硅片的光刻實(shí)驗(yàn)已經(jīng)成功驗(yàn)證了可分離式模型在不同掃描型光刻機(jī)-光刻膠工藝類型中的應(yīng)用。計(jì)算光刻的可分離式模型能夠大幅度地加快產(chǎn)品投入生產(chǎn)的速度。如果現(xiàn)有的光刻膠工藝能夠用于新型的掃描式光刻成像條件,這一可靠的模型(適用于任何掃描式光刻設(shè)備配置)只需要幾分鐘,而不是以往需要幾周的時(shí)間就能執(zhí)行。在曝光設(shè)備安裝之前,該模型就能使用在設(shè)備廠測(cè)量的精確設(shè)備參數(shù),愈早能建立精確的模型,就能夠同時(shí)、平行地來確定設(shè)計(jì)規(guī)則、RET策略、OPC開發(fā)等。你還可以發(fā)現(xiàn)有更多的選件以及能獲得最佳化的解決方案。
參考文獻(xiàn)
1. Y. Cao, Y.-W. Lu, L. Chen, J. Ye, “Optimized Hardware and Software for Fast Full-chip Simulation,”Proc. SPIE 5754, 2004.
2. P. Martin, C.J. Progler, Y.-m. Ham, B. Kasprowicz, R. Gray, J.N. Wiley, et al., “Exploring New High-Speed Mask Aware RET Verification Flows,”Proc. SPIE 5853, 2005.
3. L. Chen, Y. Cao, H.-y. Liu, W. Shao, M. Feng, Jun Ye, “Predictive Focus Exposure Modeling (FEM) for Full-chip Lithography,”Proc. SPIE 6154, 2006.
4. Y. Huang, E. Tseng, B.S.-M. Lin, C.C. Yu, C.-M. Wang, H.-Y. Liu, “Full-chip Lithography Manufacturability Check for Yield Improvement,”Proc. SPIE 6156, 2006.
5. Y. Zhang, M. Feng, H.-y. Liu, “A Focus Exposure Matrix Model for Full-chip Lithography Manufacturability Check and Optical Proximity Correction,”Proc. SPIE 6283, 2006.
6. H. Feng, J. Ye, R. Fabian Pease, “Segmentation-assisted Edge Extraction Algorithms for SEM Images,” Proc. SPIE 6349, 2006.
7. J. Vasek, et al., “Using Design Intent to Qualify and Control Lithography Manufacturing,”Proc. SPIE 6156, 2006.
8. F. Foussadier, F. Sundermann, A. Vacca, J. Wiley, G. Chen, T. Takigawa, et al., “Model-based Mask Verification,” Proc. SPIE 6730, 2007. |
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